Electrostatic discharge (ESD) protection circuits use clamps triggered by ESD events safely discharge a protected pad or node. Dual direction or bidirectional clamp circuits provide protection for both positive and negative ESD voltages, while allowing the signal to swing positive and negative during normal operation. Dual direction ESD protection is adopted in many applications. For example, dual direction ESD protection is applicable to audio signal inputs, interfaces and level shifters. ESD clamps implemented as diacs or other thyristors in a CMOS process using deep n-wells or the like often have high threshold or trigger voltages, and are thus challenging for protecting low voltage circuitry. The trigger voltage of dual direction clamps with a p+/n-well junction breakdown scheme can be lowered by using polysilicon gates to improve the ESD clamp efficiency. When proper bias is provided to the gate, channel leakage can be prevented, thereby keeping the clamp circuit off during normal operation. For a PMOS gate structure in a clamp circuit using a p+/n-well junction breakdown to trigger ESD protection, the gate is biased above the PMOS threshold voltage during normal operation. However, biasing the clamp circuit gate at a positive supply rail can cause gate oxide integrity (GOI) problems during normal operation where negative voltages are applied to the protected pad. Alternatively, two separate unidirectional circuits may be used to protect each node with positive and negative signaling. However, such an approach will likely increase die size of an integrated circuit (IC).